Non-volatile memory having first and second leday circuits, and electronic system and method

Abstract

A non-volatile memory includes a row decoder including, for each word-line, a respective pull-up connected to a first supply voltage and a switching circuit for selectively connecting one of the word-lines to ground. The row decoder includes a demultiplexer connected to a second supply voltage smaller than the first, and configured to assert an enable signal as a function of an address signal. The switching circuit includes two n-channel FETs connected in series between the word-line and ground, with the gate terminal of one FET connected to a first signal and the gate terminal of the other FET connected to a second voltage. A bias circuit is configured to set the voltage between the two FETs to the second voltage when the FETs are opened. The switching circuit includes a p-channel FET connected between the word-line and the second voltage, and a gate terminal connected to a second signal.