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For the Inventor, By the Inventor

Yokohama, Japan

Ayako Nakano

This inventor holds 11 USPTO granted patents and 2 published patent applications. Top assignee: Kabushiki Kaisha Toshiba. Active years: 2006-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ayako Nakano. Retrieved from https://idiyas.com/inventor/ayako-nakano

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 11 

% Patents Active = 18.2

Average Co-Inventor Count = 2.7

ph-index = 3

Forward Citations = 28(Granted Patents)


Location History:

  • Chiba, JP (2008)
  • Yokohama, JP (2006 - 2011)

Company Filing History:

goldMedal11 out of 53,276 
 
Kabushiki Kaisha Toshiba
 patents

Years Active: 2006-2011

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11 patents (USPTO):Explore Patents
1. 8042067 - Pattern forming method and system, and method of manufacturing a semiconductor device (2011-10-18),
2. 7984390 - Data processing method in semiconductor device, program of the same, and manufacturing method of semiconductor device (2011-07-19),
3. 7859665 - Polarization analyzing system, exposure method, and method for manufacturing semiconductor device (2010-12-28),
4. 7770145 - Semiconductor device pattern creation method, pattern data processing program, and semiconductor device manufacturing method (2010-08-03),
5. 7716617 - Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device (2010-05-11),
6. 7700997 - Semiconductor memory device (2010-04-20),
7. 7534533 - Polarization analyzing system, exposure method, and method for manufacturing semiconductor device (2009-05-19),
8. 7463347 - Simulator of optical intensity distribution, computer implemented method for simulating the optical intensity distribution, method for collecting mask pattern, and computer program product for the simulator (2008-12-09),
9. 7402363 - Pattern forming method and system, and method of manufacturing a semiconductor device (2008-07-22),
10. 7002665 - Lithography simulation method, mask pattern correction method, and substrate topography correction method (2006-02-21),
11. 7000215 - Method of and computer program product for designing patterns, and method of manufacturing semiconductor device (2006-02-14),

Title: Ayako Nakano: Innovator in Semiconductor Technology

Introduction

Ayako Nakano is a prominent inventor based in Yokohama, Japan. She has made significant contributions to the field of semiconductor technology, holding a total of 11 patents. Her innovative work has advanced the methods used in semiconductor manufacturing and design.

Latest Patents

Among her latest patents is a pattern forming method and system, which focuses on creating desired patterns on semiconductor substrates. This method involves extracting patterns from layers, calculating distances between them, and ensuring they meet predetermined process variations. If the patterns do not satisfy the allowable margins, the method allows for corrections to be made. Another notable patent is a data processing method in semiconductor devices, which includes changing the connection angles of wiring to enhance design data.

Career Highlights

Ayako Nakano has worked with notable companies such as Kabushiki Kaisha Toshiba and Toshiba Corporation. Her experience in these organizations has allowed her to refine her skills and contribute to groundbreaking advancements in semiconductor technology.

Collaborations

She has collaborated with talented individuals in her field, including Toshiya Kotani and Takashi Sato. These partnerships have fostered innovation and have been instrumental in her successful projects.

Conclusion

Ayako Nakano's contributions to semiconductor technology through her patents and collaborations highlight her as a leading figure in the industry. Her work continues to influence the future of semiconductor manufacturing and design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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