Kabushiki Kaisha Toshiba

Kabushiki Kaisha Tosbhia

Ayako Nakano

Toshiya Kotani

Takashi Sato

Satoshi Tanaka

Tadahito Fujisawa

Hiromitsu Mashita

Atsushi Maesono

Koji Hashimoto

Takuya Futatsuyama

Tsuyoshi Shibata

Yuji Kobayashi

Atsushi Watanabe

A pattern forming method of forming a desired pattern on a semiconductor substrate is disclosed, which comprises extracting a first pattern of a layer, extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern, calculating a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation, determining whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns, and correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin.

Pattern forming method and system, and method of manufacturing a semiconductor device

A design data processing method in a semiconductor device includes extracting, from design data, a graphic in which there exist a first wiring and a second wiring which is orthogonal to the first wiring, and changing a portion where the first wiring is orthogonal to the second wiring to make connection at an angle other than 90 degrees, thereby preparing new design data.

Data processing method in semiconductor device, program of the same, and manufacturing method of semiconductor device

A polarization analyzing system includes a data collector collecting information on resist patterns formed over step patterns by first and second lights, the first and second lights being polarized parallel and perpendicular to the step patterns, a residual resist analyzer obtaining first and second relations between a ratio of a space to a line width of the resist patterns and the first and second residues, the first and second residues remaining at orthogonal points of the step patterns and the resist patterns, and a direction chooser choosing an optimum polarization direction reducing residues by comparing the first and second relations.

Polarization analyzing system, exposure method, and method for manufacturing semiconductor device

A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance.

Semiconductor device pattern creation method, pattern data processing program, and semiconductor device manufacturing method

A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (&#x2267;2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern Nand at least one circuit pattern Ni (i&#x2267;2) arranged in one direction different from longitudinal direction of the circuit pattern Nthe at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern Nand in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction.

Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device

According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines; and electrical connections for connection said word lines and sources or drains of said first transistors, said electrical connections being formed of both first wirings of a first wiring layer formed above said first gate wiring layer and second wirings of a second wiring layers formed above said first wiring layer.

Semiconductor memory device

A simulator of an optical intensity distribution includes a field divider dividing an exposure field on a substrate into a first and second fields, the first field being to be directly exposed to a light incident at the maximum incident angle, the second field being prevented from being directly exposed to the light by a protrusion on the substrate, a first optical intensity calculator calculating an optical intensity of the first field by using a direct incident light component of the light, a second optical intensity calculator calculating an optical intensity of the second field by using a reflected light component of the light reflected from a sidewall of the protrusion, and a projected image simulation engine simulating an optical intensity distribution of a projected image of a mask pattern on the substrate, based on the optical intensities of the first field and the second field.

Simulator of optical intensity distribution, computer implemented method for simulating the optical intensity distribution, method for collecting mask pattern, and computer program product for the simulator

An aspect of the present invention provides simulation that includes dividing a surface of a substrate onto which light that is focused at an aperture angle by a projection lens is shone into a first region onto which all of the light strikes and a second region onto which a portion of the light strikes, calculating an intensity of the light shone onto the first region, and calculating an intensity of the light shone onto the second region.

Lithography simulation method, mask pattern correction method, and substrate topography correction method

A method of designing patterns has preparing a mask pattern used in a lithography process for transferring a circuit pattern intersecting with a step pattern on a substrate which has the step pattern designed thereon, and applying correction patterns to the mask pattern in accordance with correction rules considering a shape of the step pattern, the correction patterns being applied at intersections of edges of the circuit pattern and the step pattern and in the vicinity of the intersections.

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Yokohama, Japan

Ayako Nakano