The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7716617 B1

PDF
Full Text
Expired
Date of Patent:
May. 11, 2010

Filed:

Dec. 13, 2005
Applicants:

Hiromitsu Mashita, Sagamihara, JP;

Toshiya Kotani, Machida, JP;

Atsushi Maesono, Yokohama, JP;

Ayako Nakano, Yokohama, JP;

Tadahito Fujisawa, Yokkaichi, JP;

Inventors:

Hiromitsu Mashita, Sagamihara, JP;

Toshiya Kotani, Machida, JP;

Atsushi Maesono, Yokohama, JP;

Ayako Nakano, Yokohama, JP;

Tadahito Fujisawa, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03K 19/177 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (≧2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern Nand at least one circuit pattern Ni (i≧2) arranged in one direction different from longitudinal direction of the circuit pattern Nthe at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern Nand in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction.


Find Patent Forward Citations

Mashita, Hiromitsu. (2010). Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device (U.S. Patent No. 7716617). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7716617

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