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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Andrew P Edwards

This inventor holds 26 USPTO granted patents and 14 published patent applications, primarily in Semiconductor Devices. Top assignees: Semiconductor Components Industries, LLC, Nexgen Power Systems, Inc.. Active years: 2022-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Andrew P Edwards. Retrieved from https://idiyas.com/inventor/andrew-p-edwards

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 26 

% Patents Active = 100.0

Average Co-Inventor Count = 4.6

ph-index = 2

Forward Citations = 9(Granted Patents)


Company Filing History:

goldMedal17 out of 3,725 
 
Semiconductor Components Industries, LLC
 patents
silverMedal9 out of 20 
 
Nexgen Power Systems, Inc.
 patents

Years Active: 2022-2026

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Areas of Expertise:
FinFET Technology
GaN Vertical Devices
JFET Isolation
Voltage Clamp
Electrical Conductors
Edge Termination
Fiducials Fabrication
Etch Depth Control
Power FET Arrays
Selective Area Growth
Regrowth Uniformity
High Voltage Devices
26 patents (USPTO):Explore Patents
1. 12738730 - Method and system for a fin-based voltage clamp (2026-09-15),
2. 12598805 - Vertical fin-based field effect transistor (FinFET) with connected fin tips (2026-04-07),
3. 12588239 - Method and system for routing of electrical conductors over neutralized power FETS (2026-03-24),
4. 12527028 - Negative charge extraction structure for edge termination (2026-01-13),
5. 12520513 - Regrowth uniformity in GaN vertical devices (2026-01-06),
6. 12484294 - Vertical fin-based field effect transistor (FinFET) with neutralized fin tips (2025-11-25),
7. 12381159 - Method and system for fabricating fiducials for processing of semiconductor devices (2025-08-05),
8. 12334352 - Method and system for etch depth control in III-V semiconductor devices (2025-06-17),
9. 12274086 - Fabrication method for JFET with implant isolation (2025-04-08),
10. 12272654 - Method and system for fabricating fiducials using selective area growth (2025-04-08),
11. 12262557 - Methods and systems to improve uniformity in power FET arrays (2025-03-25),
12. 12224344 - Method and system for control of sidewall orientation in vertical gallium nitride field effect transistors (2025-02-11),
13. 12155204 - Method and system for fin-based voltage clamp (2024-11-26),
14. 12136645 - Coupled guard rings for edge termination (2024-11-05),
15. 12125914 - Method and system for fabrication of a vertical fin-based field effect transistor (2024-10-22),

Title: The Innovative Journey of Andrew P Edwards

Introduction: Andrew P Edwards is a distinguished inventor based in Santa Clara, CA (US), known for his groundbreaking contributions to various fields.

Latest Patents: Andrew P Edwards holds several patents in the areas of technology, healthcare, and sustainable energy, showcasing his versatility and forward-thinking approach.

Career Highlights: With a career spanning over two decades, Andrew P Edwards has worked with leading research institutions and companies, consistently pushing the boundaries of innovation. His work has been instrumental in shaping the future of multiple industries.

Collaborations: Throughout his career, Andrew P Edwards has collaborated with top universities, renowned inventors, and forward-looking companies, fostering a culture of creativity and excellence in all his projects.

Conclusion: Andrew P Edwards stands as a beacon of innovation, with a legacy that continues to inspire the next generation of inventors and creators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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