The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2024

Filed:

Apr. 20, 2023
Applicant:

Semiconductor Components Industries, Llc, Scottsdale, AZ (US);

Inventors:

Andrew J. Walker, Santa Clara, CA (US);

Clifford Drowley, Santa Clara, CA (US);

Subhash Srinivas Pidaparthi, Santa Clara, CA (US);

Andrew P. Edwards, Santa Clara, CA (US);

Shahin Sharifzadeh, Santa Clara, CA (US);

Joseph Tandingan, Santa Clara, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H02H 9/045 (2013.01); H01L 27/0274 (2013.01);
Abstract

A method of clamping a voltage includes providing a fin-based field effect transistor (FinFET) device. The FinFET device includes an array of FinFETs. Each FinFET includes a source contact electrically coupled to a fin and a gate contact. The method also includes applying the voltage to the source contact and applying a second voltage to the gate contact. The voltage is greater than the second voltage. The method further includes increasing the voltage to a threshold voltage and conducting current from the source contact to the gate contact in response to the voltage reaching the threshold voltage.


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