Hillsboro, OR, United States of America

Amit Agarwal

This inventor holds 37 USPTO granted patents and 16 published patent applications and 4 EPO patents, primarily in Register File Technology. Top assignee: Intel Corporation. Active years: 2007-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Amit Agarwal. Retrieved from https://idiyas.com/inventor/amit-agarwal-kxr7eldc

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 37 

% Patents Active = 62.2

 

Average Co-Inventor Count = 4.0

ph-index = 7

Forward Citations = 115(Granted Patents)


Location History:

  • West Lafayette, IN (US) (2007)
  • Hillsboro, OR (US) (2008 - 2023)

Company Filing History:


Years Active: 2007-2026

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Areas of Expertise:
Register Files
Deep Neural Networks
Low Power Flip-Flops
Voltage Level Shifter
Clock Gate Circuit
Scene Reconstruction
Multi-Buffered Circuits
Aging Tolerant
Scan Multiplexer
Voltage Mode Pre-Charging
Configurable Logic Blocks
Global Bitline Accelerator
37 patents (USPTO):Explore Patents

Title: Amit Agarwal: Innovator in Scene Reconstruction and Power Optimization

Introduction

Amit Agarwal, based in Hillsboro, Oregon, is a prolific inventor with an impressive portfolio of 32 patents to his name. His contributions primarily focus on advancements in technology that improve efficiency in electronics and computational methods. This article highlights his latest patents and career achievements, showcasing his innovative spirit and collaborative efforts in the tech industry.

Latest Patents

Amit's latest inventions include a groundbreaking method titled "Apparatus and method for approximate trilinear interpolation for scene reconstruction." This method enhances 3D space understanding by dividing it into a voxel grid and utilizing distance values to improve interpolation efficiency through sophisticated ray-stepping techniques.

Another significant patent is for a "Low power flip-flop with reduced parasitic capacitance." This invention introduces a parasitic-aware, single-edge triggered flip-flop that optimizes clock power consumption. By leveraging process-circuit co-optimization, Amit's design permits substantial power reduction through innovative layout changes, resulting in enhanced performance across electronic devices.

Career Highlights

Amit Agarwal is a key contributor at Intel Corporation, a leading technology company renowned for its advancements in semiconductor manufacturing and computing technology. His role at Intel reflects a commitment to innovation, driving the company toward more efficient and powerful solutions that meet the demands of modern technology.

Collaborations

Throughout his career, Amit has collaborated with talented peers, including Steven Hsu and Ram K Krishnamurthy. Their collective expertise fosters a dynamic environment for innovation, allowing for insightful exchanges that propel forward-thinking solutions in their projects.

Conclusion

Amit Agarwal's work exemplifies the essence of innovation in the technology sector. With numerous patents that address both computational methods and power optimization, he continues to make significant contributions that enhance electronic design and application. His collaborations and position at Intel Corporation showcase a dedicated pursuit of excellence in the field of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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