The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2026
Filed:
Sep. 23, 2022
Intel Corporation, Santa Clara, CA (US);
Raymond Jit-Hung Sung, San Francisco, CA (US);
Deepak Abraham Mathaikutty, Chandler, AZ (US);
Amit Agarwal, Hillsboro, OR (US);
David Thomas Bernard, Kilcullen, IE;
Steven Hsu, Lake Osego, OR (US);
Martin Power, Dublin, IE;
Conor Byrne, Dublin, IE;
Arnab Raha, San Jose, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A memory array of a compute tile may store activations or weights of a DNN. The memory array may include databanks for storing contexts, context MUXs, and byte MUXs. A databank may store a context with flip-flop arrays, each of which includes a sequence of flip-flops. A logic gate and an ICG unit may gate flip-flops and control whether states of the flip-flops can be changed. The data gating can prevent a context not selected for the databank from inadvertently toggling and wasting power A context MUX may read a context from different flip-flop arrays in a databank based on gray-coded addresses. A byte MUX can combine bits from different bytes in a context read by the context MUX. The memory array may be implemented with bit packing to reduce distance between the context MUX and byte MUX to reduce lengths of wires connecting the context MUXs and byte MUXs.