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For the Inventor, By the Inventor

West Lafayette, IN, United States of America

Arnab Raha

USPTO Granted Patents = 14 

 

Average Co-Inventor Count = 4.5

ph-index = 1

Forward Citations = 1(Granted Patents)


Location History:

  • West Lafayette, IN (US) (2020)
  • Santa Clara, CA (US) (2021 - 2024)

Company Filing History:

goldMedal12 out of 54,781 
 
Intel Corporation
 patents
silverMedal2 out of 2,664 
 
Purdue Research Foundation
 patents

Years Active: 2020-2025

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14 patents (USPTO):Explore Patents
1. 12438553 - Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectors (2025-10-07),
2. 12386618 - Multi-buffered register files with shared access circuits (2025-08-12),
3. 12367380 - System and method for balancing sparsity in weights for accelerating deep neural networks (2025-07-22),
4. 12288153 - Schedule-aware tensor distribution module (2025-04-29),
5. 12242861 - Methods and apparatus to load data within a machine learning accelerator (2025-03-04),
6. 12229673 - Sparsity-aware datastore for inference processing in deep neural network architectures (2025-02-18),
7. 12147836 - Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning accelerators (2024-11-19),
8. 12141683 - Performance scaling for dataflow deep neural network hardware accelerators (2024-11-12),
9. 11922178 - Methods and apparatus to load data within a machine learning accelerator (2024-03-05),
10. 11907827 - Schedule-aware tensor distribution module (2024-02-20),
11. 11804851 - Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectors (2023-10-31),
12. 10963975 - System architecture and method of processing data therein (2021-03-30),
13. 10671744 - Lightweight trusted execution for internet-of-things devices (2020-06-02),
14. 10591902 - Microcontroller energy management system (2020-03-17),

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