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For the Inventor, By the Inventor

West Lafayette, IN, United States of America

Arnab Raha

This inventor holds 17 USPTO granted patents and 41 published patent applications and 3 EPO patents, primarily in Deep Learning Hardware. Top assignees: Intel Corporation, Purdue Research Foundation. Active years: 2020-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Arnab Raha. Retrieved from https://idiyas.com/inventor/arnab-raha

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 17 

% Patents Active = 100.0

 

Average Co-Inventor Count = 4.7

ph-index = 1

Forward Citations = 2(Granted Patents)


Location History:

  • West Lafayette, IN (US) (2020)
  • Santa Clara, CA (US) (2021 - 2024)

Company Filing History:

goldMedal15 out of 56,394 
 
Intel Corporation
 patents
silverMedal2 out of 2,786 
 
Purdue Research Foundation
 patents

Years Active: 2020-2026

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Areas of Expertise:
Deep Learning
DNN Accelerators
Convolutional Neural Networks
Data Reuse
Sparse Data Processing
Tensor Distribution
Performance Scaling
Energy Management
Trusted Execution
Microcontrollers
Register Files
Inference Processing
17 patents (USPTO):Explore Patents
1. 12775838 - Data reuse in deep learning (2026-10-27),
2. 12566212 - Power efficient register files for deep neural network (DNN) accelerator (2026-03-03),
3. 12554962 - Configurable processor element arrays for implementing convolutional neural networks (2026-02-17),
4. 12438553 - Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectors (2025-10-07),
5. 12386618 - Multi-buffered register files with shared access circuits (2025-08-12),
6. 12367380 - System and method for balancing sparsity in weights for accelerating deep neural networks (2025-07-22),
7. 12288153 - Schedule-aware tensor distribution module (2025-04-29),
8. 12242861 - Methods and apparatus to load data within a machine learning accelerator (2025-03-04),
9. 12229673 - Sparsity-aware datastore for inference processing in deep neural network architectures (2025-02-18),
10. 12147836 - Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning accelerators (2024-11-19),
11. 12141683 - Performance scaling for dataflow deep neural network hardware accelerators (2024-11-12),
12. 11922178 - Methods and apparatus to load data within a machine learning accelerator (2024-03-05),
13. 11907827 - Schedule-aware tensor distribution module (2024-02-20),
14. 11804851 - Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectors (2023-10-31),
15. 10963975 - System architecture and method of processing data therein (2021-03-30),

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Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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