The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2024

Filed:

Apr. 30, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Arnab Raha, Santa Clara, CA (US);

Debabrata Mohapatra, Santa Clara, CA (US);

Gautham Chinya, Sunnyvale, CA (US);

Guruguhanathan Venkataramanan, Livermore, CA (US);

Sang Kyun Kim, San Jose, CA (US);

Deepak Mathaikutty, Santa Clara, CA (US);

Raymond Sung, San Francisco, CA (US);

Cormac Brick, San Francisco, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/10 (2006.01); G06F 9/30 (2018.01); G06N 3/04 (2023.01); G06N 3/063 (2023.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 9/3001 (2013.01); G06N 3/04 (2013.01);
Abstract

Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. Disclosed embodiments include static MAC scaling arrangement, which includes architectures and techniques for scaling the performance per unit of power and performance per area of HW accelerators. Disclosed embodiments also include dynamic MAC scaling arrangement, which includes architectures and techniques for dynamically scaling the number of active multiply-and-accumulate (MAC) within an HW accelerator based on activation and weight sparsity. Other embodiments may be described and/or claimed.


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