The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Aug. 30, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Steven K. Hsu, Lake Oswego, OR (US);

Amit Agarwal, Hillsboro, OR (US);

Ram K. Krishnamurthy, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); H03K 3/037 (2013.01); H03K 3/0372 (2013.01); H03K 19/01855 (2013.01); H03K 19/018514 (2013.01); H03K 19/018528 (2013.01);
Abstract

Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.


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