The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2023
Filed:
Dec. 26, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Steven Hsu, Lake Oswego, OR (US);
Amit Agarwal, Hillsboro, OR (US);
Simeon Realov, Portland, OR (US);
Ram Krishnamurthy, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 5/135 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0016 (2013.01); G11C 7/222 (2013.01); H03K 3/012 (2013.01); H03K 3/0372 (2013.01); H03K 5/135 (2013.01); H03K 19/0013 (2013.01);
Abstract
A parasitic-aware single-edge triggered flip-flop reduces clock power through layout optimization, enabled through process-circuit co-optimization. The static pass-gate master-slave flip-flop utilizes novel layout optimization enabling significant power reduction. The layout removes the clock poly over notches in the diffusion area. Poly lines implement clock nodes. The poly lines are aligned between n-type and p-type active regions.