The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 2021
Filed:
Dec. 23, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Amit Agarwal, Hillsboro, OR (US);
Steven Hsu, Lake Oswego, OR (US);
Anupama Ambardar Thaploo, Folsom, CA (US);
Simeon Realov, Portland, OR (US);
Ram Krishnamurthy, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G01R 31/317 (2006.01); H03K 3/037 (2006.01); G01R 31/3177 (2006.01); H03K 3/038 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318541 (2013.01); G01R 31/317 (2013.01); G01R 31/3177 (2013.01); G01R 31/31723 (2013.01); G01R 31/318525 (2013.01); G01R 31/318536 (2013.01); G01R 31/318583 (2013.01); G01R 31/318586 (2013.01); G01R 31/318597 (2013.01); H03K 3/038 (2013.01); H03K 3/0372 (2013.01);
Abstract
A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.