The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Apr. 01, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Amit Agarwal, Hillsboro, OR (US);

Steven Hsu, Lake Oswego, OR (US);

Simeon Realov, Portland, OR (US);

Mahesh Kumashikar, Bangalore, IN;

Ram Krishnamurthy, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 3/037 (2006.01); G01R 31/3177 (2006.01); H03K 3/038 (2006.01); H03K 19/20 (2006.01); H03K 3/3562 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0372 (2013.01); G01R 31/3177 (2013.01); H03K 3/038 (2013.01); H03K 3/35625 (2013.01); H03K 19/20 (2013.01);
Abstract

A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.


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