Hyogo, Japan

Akinobu Teramoto

This inventor holds 9 USPTO granted patents. Top assignees: Mitsubishi Denki Kabushiki Kaisha, Renesas Technology Corp.. Active years: 2001-2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Akinobu Teramoto. Retrieved from https://idiyas.com/inventor/akinobu-teramoto-ahwrp3g5

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 55.6

Average Co-Inventor Count = 2.5

ph-index = 3

Forward Citations = 20(Granted Patents)


Location History:

  • Tokyo, JP (2001 - 2004)
  • Hyogo, JP (2002 - 2004)

Company Filing History:


Years Active: 2001-2004

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9 patents (USPTO):Explore Patents

Title: Akinobu Teramoto: Innovator in Semiconductor Technology

Introduction

Akinobu Teramoto is a renowned inventor based in Hyogo, Japan, with a remarkable portfolio of nine patents to his name. His contributions to the field of semiconductor technology have significantly advanced the efficiency and functionality of devices utilized in various applications.

Latest Patents

Among Teramoto's latest patents is a semiconductor device that includes a nitride layer. This innovative device features an n-type semiconductor substrate that comprises a source region and a drain region on its main surface. To enhance performance, a high-permittivity insulator film, which includes a high permittivity material, is intricately designed to cover the upper side of the region situated between the source and drain regions. Furthermore, the device integrates a boron-doped gate electrode positioned above the high-permittivity insulator film, complemented by a high-permittivity nitride layer placed between the insulator and the gate electrode.

Another significant patent pertains to the method of manufacturing the semiconductor device that incorporates a memory cell. The process initiates with the formation of a gate oxide film on the substrate, followed by the creation of gate interconnections composed of a first silicon film, a silicide film, and a dielectric film atop the gate oxide. An impurity is subsequently implanted into the substrate using the gate interconnections as a mask, facilitating the formation of a first diffusion layer. The method continues with the deposition of a second silicon film over the substrate, covering the gate interconnections, which is then thermally oxidized to produce a thermal oxide film. An interlayer dielectric film is finally established on the thermal oxide film.

Career Highlights

Teramoto's professional journey includes pivotal roles at major corporations, specifically Mitsubishi Electric Corporation and Renesas Technology Corporation. His tenure at these companies focused on the development of cutting-edge semiconductor technologies, further showcasing his expertise and innovative spirit.

Collaborations

Throughout his career, Akinobu Teramoto has collaborated with other notable professionals in the field, including Kazutoshi Wakao and Takashi Terauchi. These partnerships have undoubtedly played a significant role in fostering creativity and innovation in semiconductor research and development.

Conclusion

Akinobu Teramoto stands out as a leading figure in semiconductor technology, with a solid record of patents that underline his commitment to innovation. His work not only exemplifies technical prowess but also highlights the collaborative nature of advancements in the field. As technology continues to evolve, inventors like Teramoto play a crucial role in shaping the future of electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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