The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2003
Filed:
Apr. 08, 2002
Applicant:
Inventors:
Kiyoshi Mori, Tokyo, JP;
Akinobu Teramoto, Tokyo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18238 ;
U.S. Cl.
CPC ...
H01L 2/18238 ;
Abstract
Isolation regions are formed on a silicon substrate to isolate NMOS and PMOS regions in which to form NMOS and PMOS transistors respectively. A silicon oxide film and an amorphous silicon film are formed as a gate insulating film on the silicon substrate N-type impurities are injected into the NMOS regions (FIG. A). A WSi film is formed on the amorphous silicon film and N-type impurities are injected only into the PMOS regions of the film (FIG. C). A silicon oxide film and a silicon nitride film are formed on the WSi film and then etched into gate electrodes (FIG. E).