Adam J Wright

This inventor holds 22 USPTO granted patents, primarily in Semiconductor Testing. Top assignees: Altera Corporation, Intel Corporation. Active years: 1999-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Adam J Wright. Retrieved from https://idiyas.com/inventor/adam-j-wright

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 22

% Patents Active = 27.3

Average Co-Inventor Count = 2.0

ph-index = 6

Forward Citations = 137(Granted Patents)

Location History:

San Jose, CA (US) (2006 - 2010)
Saratoga, CA (US) (2006 - 2014)
Santa Clara, CA (US) (1999 - 2022)

Company Filing History:

Years Active: 1999-2022

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Areas of Expertise:

Integrated Circuits

Semiconductor Testing

Programmable Logic Devices

Diagnostic Capabilities

Signal Skew Minimization

Test Configuration

FPGA Testing

Functional Failure Analysis

Laser Marking

Interconnect Faults

Data Protection

Configuration Loading

22 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11281195 - Integrated circuits with in-field diagnostic and repair capabilities (2022-03-22),

2. 8786301 - Apparatus for a low-cost semiconductor test interface system (2014-07-22),

3. 8779754 - Method and apparatus for minimizing skew between signals (2014-07-15),

4. 8543876 - Method and apparatus for serial scan test data delivery (2013-09-24),

5. 7940082 - Circuits and method for bypassing a static configuration in a programmable logic device to implement a dynamic multiplexer (2011-05-10),

6. 7884619 - Method and apparatus for minimizing skew between signals (2011-02-08),

7. 7795909 - High speed programming of programmable logic devices (2010-09-14),

8. 7768280 - Apparatus for a low-cost semiconductor test interface system (2010-08-03),

9. 7685485 - Functional failure analysis techniques for programmable integrated circuits (2010-03-23),

10. 7671579 - Method and apparatus for quantifying and minimizing skew between signals (2010-03-02),

11. 7546507 - Method and apparatus for debugging semiconductor devices (2009-06-09),

12. 7409669 - Automatic test configuration generation facilitating repair of programmable circuits (2008-08-05),

13. 7265573 - Methods and structures for protecting programming data for a programmable logic device (2007-09-04),

14. 7237106 - System for loading configuration data into a configuration word register by independently loading a plurality of configuration blocks through a plurality of configuration inputs (2007-06-26),

15. 7103813 - Method and apparatus for testing interconnect bridging faults in an FPGA (2006-09-05),

Title: The Innovative Journey of Adam J Wright

Introduction: Adam J Wright, a talented inventor hailing from Saratoga, CA, has made significant contributions to the field of technology with his groundbreaking inventions and patents.

Latest Patents: Adam J Wright's latest patents include a cutting-edge software application for enhancing cybersecurity measures in cloud computing systems and a revolutionary wearable device that monitors and tracks vital health metrics in real-time.

Career Highlights: Throughout his illustrious career, Adam J Wright has been recognized for his innovative spirit and problem-solving abilities. He has received multiple awards for his inventions, including the prestigious Inventor of the Year award from the Silicon Valley Inventors Association.

Collaborations: Adam J Wright has collaborated with leading tech companies and research institutions to bring his inventions to life. His partnerships have led to the development of cutting-edge products that have transformed industries and improved the lives of many.

Conclusion: Adam J Wright's passion for innovation and dedication to pushing the boundaries of technology have solidified his reputation as a pioneering inventor in the field. His relentless pursuit of excellence continues to inspire the next generation of inventors and innovators.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]