The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2010
Filed:
Oct. 30, 2003
Binh Vo, San Jose, CA (US);
Wan-pin Hung, Saratoga, CA (US);
David Huang, Fremont, CA (US);
Peter Boyle, Mountain View, CA (US);
Qi Richard Chen, Sunnyvale, CA (US);
Kaiyu Ren, San Jose, CA (US);
Adam J. Wright, San Jose, CA (US);
John Dicosola, Pleasanton, CA (US);
Laiq Chughtai, Fremont, CA (US);
Seng Yew Lim, Penang, MY;
Binh Vo, San Jose, CA (US);
Wan-Pin Hung, Saratoga, CA (US);
David Huang, Fremont, CA (US);
Peter Boyle, Mountain View, CA (US);
Qi Richard Chen, Sunnyvale, CA (US);
Kaiyu Ren, San Jose, CA (US);
Adam J. Wright, San Jose, CA (US);
John DiCosola, Pleasanton, CA (US);
Laiq Chughtai, Fremont, CA (US);
Seng Yew Lim, Penang, MY;
Altera Corporation, San Jose, CA (US);
Abstract
Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.