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Trademarks = 4

Forward Citations = 3

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8 inventors (with patents filed for the assignee):

Jiahua Zhu (2 out of 2 patents)

Yan Lu (1 out of 16 patents)

Jingbo Gao (1 out of 7 patents)

4. Yang-Trung Lin (1 out of 3 patents)

5. Tsair-Chin Lin (1 out of 11 patents)

6. Wu Huang (1 out of 2 patents)

7. Jinya Zhang (1 out of 1 patent)

8. Yong Fu (1 out of 1 patent)

8 patents: Sort by Forward Citations

1. 12124781 - Method and apparatus of compiling verification system (2024-10-22),

2. 12111753 - Method, apparatus, and storage medium for generating test cases (2024-10-08),

3. 12093752 - Processor based logic simulation acceleration and emulation system (2024-09-17),

4. 11841761 - Method and system for tracing error of logic system design (2023-12-12),

5. 11651130 - Method, device, and storage medium for simulating a design (2023-05-16),

6. 11625521 - Method, emulator, and storage media for debugging logic system design (2023-04-11),

7. 11599139 - Dynamic adjustment of root clock frequency in logic system design during verification (2023-03-07),

8. 11537504 - Realization of functional verification debug station via cross-platform record-mapping-replay technology (2022-12-27),

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USPTO Data Jan 1 1976 - Dec 23 2025

8 Patents

#49 in Nanjing

#3,050 in China

Nanjing, China

Xepic Corporation Limited