The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2023
Filed:
Sep. 02, 2021
Applicant:
Xepic Corporation Limited, Nanjing, CN;
Inventor:
Yan Lu, Shanghai, CN;
Assignee:
XEPIC CORPORATION LIMITED, Nanjing, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/333 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 11/00 (2006.01); G06F 11/36 (2006.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 11/3652 (2013.01); G06F 30/333 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01);
Abstract
A method for debugging a logic system design including a target module to be debugged. The method includes receiving a first gate-level netlist associated with the logic system design and a second gate-level netlist associated with the target module that are generated based on a description of the logic system design, obtaining runtime information of an input signal of the target module by running the first gate-level netlist, and obtaining runtime information of the target module by running the second gate-level netlist based on the runtime information of the input signal of the target module.