The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2024

Filed:

Sep. 21, 2021
Applicant:

Xepic Corporation Limited, Nanjing, CN;

Inventor:

Yong Fu, San Ramon, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/52 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/52 (2013.01); G06F 9/48 (2013.01); G06F 9/4806 (2013.01); G06F 9/4881 (2013.01); G06F 9/50 (2013.01); G06F 9/505 (2013.01); G06F 9/5061 (2013.01); G06F 9/5066 (2013.01);
Abstract

An emulation and simulation acceleration system includes a plurality of processors, wherein each of the plurality of processors is configured to run a separate simulation task in a parallel manner. Each of the plurality of processors includes a local memory for instructions and data, a memory space for saving received data from other processors of the plurality of processors. The system includes a plurality of connection channels between each processor of the plurality of processors, wherein each of the plurality of connection channels is either virtual or physical, and each of the plurality of connection channels extends through computer hardware or memory mapping. The system includes a plurality of system interfaces configured to interface with other systems for expansion to a larger system or to connect with external target system. Each of the plurality of system interfaces contains a virtual interface and a physical interface for connecting with other simulators.


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