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Sunnyvale, CA, United States of America

Syntest Technologies, Inc.

USPTO Granted Patents = 55

% Expired Patents = 92.7

Forward Citations = 631

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35 inventors (with patents filed for the assignee):

Laung-Terng Wang (35 out of 38 patents)

Xiaoqing Wen (32 out of 43 patents)

Hsin-Po Wang (17 out of 21 patents)

4. Laung-Terng (l-t) Wang (17 out of 17 patents)

5. Po-Ching Hsu (16 out of 16 patents)

6. Shianling Wu (14 out of 16 patents)

7. Shih-Chia Kao (13 out of 14 patents)

8. Meng-Chyi Lin (12 out of 19 patents)

9. Khader S Abdel-Hafez (12 out of 13 patents)

10. Shyh-Horng Lin (11 out of 13 patents)

11. Boryau (Jack) Sheu (11 out of 11 patents)

12. Hao-Jan Chao (10 out of 10 patents)

13. Zhigang Jiang (10 out of 12 patents)

14. Nur A Touba (7 out of 11 patents)

15. Fei-Sheng Hsu (6 out of 7 patents)

Core Competencies:

DFT System

Scan Compression

CAD Automation

Test Patterns

Crossing Clock-Domain Faults

Debug Techniques

3D Integrated Circuits

Mask Network Design

Integrated Circuit Testing

Self-Test

Pipelined Scan Compression

Yield Improvement

55 patents: Sort by Forward Citations

1. 9696377 - Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit (2017-07-04),

2. 9678156 - Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test (2017-06-13),

3. 9316688 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test (2016-04-19),

4. 9274168 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test (2016-03-01),

5. 9121902 - Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit (2015-09-01),

6. 9110139 - Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit (2015-08-18),

7. 9091730 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test (2015-07-28),

8. 9057763 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test (2015-06-16),

9. 9046572 - Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults (2015-06-02),

10. 9026875 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test (2015-05-05),

11. 8949299 - Method and apparatus for hybrid ring generator design (2015-02-03),

12. 8775985 - Computer-aided design system to automate scan synthesis at register-transfer level (2014-07-08),

13. 8769359 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test (2014-07-01),

14. 8667451 - Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit (2014-03-04),

15. 8543950 - Computer-aided design system to automate scan synthesis at register-transfer level (2013-09-24),

Company Overview

Syntest Technologies, Inc., based in Sunnyvale, CA, specializes in the development of advanced scan-based integrated circuits. The company focuses on enhancing design for test (DFT) systems, employing innovative techniques in scan compression and CAD automation. Their expertise extends to creating effective test patterns, addressing crossing clock-domain faults, and implementing robust debug techniques. Additionally, Syntest is involved in the design of 3D integrated circuits and mask network design, contributing to the evolution of semiconductor testing and reliability.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 13 2026

55 Patents

#92 in Sunnyvale, CA

#1,515 in California

#6,456 in US

#12,922 in the World

Sunnyvale, CA, United States of America

Syntest Technologies, Inc.

Forward Citations = 631

35 inventors:

Laung-Terng Wang (35 out of 38 patents)

Xiaoqing Wen (32 out of 43 patents)

Hsin-Po Wang (17 out of 21 patents)

4. Laung-Terng (l-t) Wang (17 out of 17 patents)

5. Po-Ching Hsu (16 out of 16 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Syntest Technologies, Inc.. Retrieved from https://idiyas.com/company/syntest-technologies

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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