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For the Inventor, By the Inventor

Hsinchu, Taiwan

Hsin-Po Wang

This inventor holds 21 USPTO granted patents and 2 published patent applications, primarily in Integrated Circuit Design. Top assignees: Syntest Technologies, Inc., Springsoft USA, Inc., Synopsys Taiwan Co., Ltd.. Active years: 2005-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hsin-Po Wang. Retrieved from https://idiyas.com/inventor/hsin-po-wang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 21 

% Patents Active = 23.8

Average Co-Inventor Count = 5.3

ph-index = 8

Forward Citations = 244(Granted Patents)


Company Filing History:

goldMedal17 out of 55 
 
Syntest Technologies, Inc.
 patents
silverMedal2 out of 22 
 
Springsoft USA, Inc.
 patents
bronzeMedal1 out of 25 
 
Synopsys Taiwan Co., Ltd.
 patents
4. 1 out of 2,611 
 
Synopsys, Inc.
 patents

Years Active: 2005-2021

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Areas of Expertise:
Integrated Circuit
DFT System
Scan Patterns
Clock Skew
Self-Test
Debug Techniques
Automated Synthesis
Post-Silicon Changes
Fault Detection
Clock-Domain
Design-for-Debug
Prototype Debug
21 patents (USPTO):Explore Patents
1. 10990743 - Creating gateway model routing sub-templates (2021-04-27),
2. 9696377 - Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit (2017-07-04),
3. 9121902 - Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit (2015-09-01),
4. 9110139 - Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit (2015-08-18),
5. 9057763 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test (2015-06-16),
6. 9026875 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test (2015-05-05),
7. 8990756 - Gateway model routing with slits on wires (2015-03-24),
8. 8769359 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test (2014-07-01),
9. 8543950 - Computer-aided design system to automate scan synthesis at register-transfer level (2013-09-24),
10. 8086982 - Methods and systems for reducing clock skew in a gated clock tree (2011-12-27),
11. 8015522 - System for implementing post-silicon IC design changes (2011-09-06),
12. 7904773 - Multiple-capture DFT system for scan-based integrated circuits (2011-03-08),
13. 7779323 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test (2010-08-17),
14. 7721173 - Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit (2010-05-18),
15. 7552373 - Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit (2009-06-23),

Title: Inventor Hsin-Po Wang

Introduction: Hsin-Po Wang is a renowned inventor based in Hsinchu, Taiwan, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Wang's latest patents focus on advancements in semiconductor technology, particularly in the development of cutting-edge microchips for various electronic devices.

Career Highlights: With a career spanning over two decades, Wang has worked with leading tech companies and research institutions, playing a key role in the creation of innovative solutions that have shaped the industry.

Collaborations: Throughout his career, Wang has collaborated with top engineers, scientists, and researchers, fostering a culture of creativity and excellence that has led to numerous successful projects and inventions.

Conclusion: Hsin-Po Wang's dedication to pushing the boundaries of technology and his passion for innovation continue to inspire the next generation of inventors and shape the future of the tech industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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