Syntest Technologies, Inc.

Springsoft Usa, Inc.

Synopsys, Inc.

Synopsys Taiwan Co., Ltd.

Hsin-Po Wang

Xiaoqing Wen

Meng-Chyi Lin

Shih-Chia Kao

Laung-Terng Wang

Po-Ching Hsu

Shyh-Horng Lin

Hao-Jan Chao

Laung-Terng (l-t) Wang

Khader S Abdel-Hafez

Fei-Sheng Hsu

Sen-Wei Tsai

Chi-Chan Hsu

Ta-Chia Yeh

Xiaqing Wen

Augusli Kifli

Ming-Tung Chang

Song Yuan

Yu-Sheng Lu

Chia-Ming Chang

Fong-Yuan Chang

Chao-Min Wang

Shih-Hsu Huang

Hung-Shih Wang

Sung-Han Tsai

Laung-Terng (l -t) Wang

Luang-Terng Wang

Jaehee Lee

Yuan-Kai Ho

Jia-Zong Lin

Yi-Der Lin

Ru Lin Yang

Chun-Cheng Chi

Hsueh Liang Hsu

Laung-Terng (l T) Wang

A computer implemented method for routing a multitude of conductors through a first routing area on a planar surface is presented. The method includes receiving data representing the first routing area bounded by two opposite longitudinal sides each having a different number of a multitude of first vertices. The first routing area includes one or more blockages. The method further includes determining one or more locations on at least one of the two opposite longitudinal sides for adding one or more second vertices, and decomposing the first routing area into a multitude of second routing areas each not including any of the one or more blockages. The method further includes performing a gateway model routing (GMR) of the multitude of conductors in each of the multitude of second routing areas using the multitude of first vertices and the added one or more second vertices.

Creating gateway model routing sub-templates

A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N&#x3e;1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

A computer-implemented method for routing at least one conductor includes generating the at least one conductor within a bounded region on a planar surface in accordance with a template, and placing at least one slit in the conductor when the conductor overlaps a specified region of the bounded region in accordance with a specified pattern.

Gateway model routing with slits on wires

A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

Computer-aided design system to automate scan synthesis at register-transfer level

Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements.

Methods and systems for reducing clock skew in a gated clock tree

An engineering change order (ECO) modifying an IC having spare cell instances is implemented by converting active cell instances implementing portions of the IC to be deleted into additional spare cell instances, by creating a technology independent behavioral model of portions of the IC to be added, by selecting spare cell instances to implement the behavior model, and by routing nets to the selected spare cell instances in a way that minimizes a number of metal layers of the IC that are modified.

System for implementing post-silicon IC design changes

A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N&#x3e;1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

Multiple-capture DFT system for scan-based integrated circuits

A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N&#x3e;1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

Growing community of inventors

Hsinchu, Taiwan

Hsin-Po Wang