The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2011
Filed:
Mar. 04, 2009
Chia-ming Chang, Kaohsiung, TW;
Shih-hsu Huang, Taichung, TW;
Yuan-kai Ho, Taipei, TW;
Jia-zong Lin, Taoyuan, TW;
Hsin-po Wang, Hsinchu, TW;
Yu-sheng LU, Hsinchu, TW;
Chia-Ming Chang, Kaohsiung, TW;
Shih-Hsu Huang, Taichung, TW;
Yuan-Kai Ho, Taipei, TW;
Jia-Zong Lin, Taoyuan, TW;
Hsin-Po Wang, Hsinchu, TW;
Yu-Sheng Lu, Hsinchu, TW;
Springsoft USA, Inc., San Jose, CA (US);
Abstract
Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements.