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For the Inventor, By the Inventor

Hsinchu, Taiwan

Po-Ching Hsu

USPTO Granted Patents = 16 

Average Co-Inventor Count = 4.5

ph-index = 6

Forward Citations = 178(Granted Patents)


Company Filing History:

goldMedal16 out of 55 
 
Syntest Technologies, Inc.
 patents

Years Active: 2006-2017

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16 patents (USPTO):Explore Patents
1. 9678156 - Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test (2017-06-13),
2. 9316688 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test (2016-04-19),
3. 9274168 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test (2016-03-01),
4. 9091730 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test (2015-07-28),
5. 9057763 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test (2015-06-16),
6. 9046572 - Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults (2015-06-02),
7. 9026875 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test (2015-05-05),
8. 8769359 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test (2014-07-01),
9. 7779323 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test (2010-08-17),
10. 7444567 - Method and apparatus for unifying self-test with scan-test during prototype debug and production test (2008-10-28),
11. 7434126 - Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults (2008-10-07),
12. 7284175 - Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques (2007-10-16),
13. 7260756 - Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test (2007-08-21),
14. 7191373 - Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques (2007-03-13),
15. 7058869 - Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits (2006-06-06),

Title: Innovator Spotlight: Po-Ching Hsu's Contributions to Fault Detection

Introduction: Po-Ching Hsu, an accomplished inventor based in Hsinchu, Taiwan, has made significant contributions to the field of integrated circuit technology. With 16 patents to his name, Hsu's innovations focus on enhancing the reliability and performance of electronic systems, particularly in the detection of faults across multiple clock domains.

Latest Patents: Hsu's latest patents include two notable innovations: the "Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test" and the "Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test." Both patents detail methods for providing ordered capture clocks to efficiently detect or locate faults in integrated circuits. These techniques involve generating and shifting test stimuli into scan cells during operations, applying capture clocks in a sequence that prevents simultaneous triggering, and analyzing the output responses to identify faults within the system.

Career Highlights: Po-Ching Hsu is currently employed at Syntest Technologies, Inc., where he continues to push the boundaries of innovation in fault detection technology. His expertise in design for testability (DFT) has played a crucial role in the advancement of integrated circuit reliability.

Collaborations: Hsu collaborates with other esteemed professionals in the field, including Xiaoqing Wen and Laung-Terng Wang. Together, they contribute to the development of pioneering solutions that enhance the testing and diagnostics of electronic systems.

Conclusion: Po-Ching Hsu's work exemplifies the impact of innovative thinking in addressing complex challenges in the realm of integrated circuits. With multiple patents showcasing his expertise in fault detection, Hsu continues to inspire future advancements in electronic engineering. His contributions not only reflect his commitment to innovation but also underscore the importance of collaboration in achieving groundbreaking results.

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