The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2007
Filed:
Feb. 27, 2002
Laung-terng (L.-t.) Wang, Sunnyvale, CA (US);
Ming-tung Chang, Hsinchu, TW;
Shyh-horng Lin, Taipei, TW;
Hao-jan Chao, Taoyuan, TW;
Jaehee Lee, San Jose, CA (US);
Hsin-po Wang, Hsinchu, TW;
Xiaoqing Wen, Sunnyvale, CA (US);
Po-ching Hsu, Hsinchu, TW;
Shih-chia Kao, Taipei, TW;
Meng-chyi Lin, Taoyuan, TW;
Sen-wei Tsai, Hsinchu, TW;
Chi-chan Hsu, Hsinchu, TW;
Laung-Terng (L.-T.) Wang, Sunnyvale, CA (US);
Ming-Tung Chang, Hsinchu, TW;
Shyh-Horng Lin, Taipei, TW;
Hao-Jan Chao, Taoyuan, TW;
Jaehee Lee, San Jose, CA (US);
Hsin-Po Wang, Hsinchu, TW;
Xiaoqing Wen, Sunnyvale, CA (US);
Po-Ching Hsu, Hsinchu, TW;
Shih-Chia Kao, Taipei, TW;
Meng-Chyi Lin, Taoyuan, TW;
Sen-Wei Tsai, Hsinchu, TW;
Chi-Chan Hsu, Hsinchu, TW;
Syntest Technologies, Inc., Sunnyvale, CA (US);
Abstract
A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.