For the Inventor, By the Inventor

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Tarrytown, NY, United States of America

Philips Semiconductor, Inc.

USPTO Granted Patents = 17

EPO Patents = 1

Forward Citations = 204

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28 inventors (with patents filed for the assignee):

David Howard Ziger (3 out of 42 patents)

Emmanuel De Muizon (2 out of 10 patents)

Rao Venkateswara Annapragada (2 out of 18 patents)

4. Paul S Levy (1 out of 44 patents)

5. David K Cassetti (1 out of 20 patents)

6. Jeffrey W Lutze (1 out of 122 patents)

7. Faran Nouri (1 out of 13 patents)

8. Jerry Michael Rose (1 out of 4 patents)

9. Pierre Leroux (1 out of 31 patents)

10. James A Cunningham (1 out of 34 patents)

11. Landon B Vines (1 out of 20 patents)

12. Tammy D Zheng (1 out of 13 patents)

13. Daniel C Baker (1 out of 11 patents)

14. Albert H Liu (1 out of 6 patents)

15. Swaroop Adusumilli (1 out of 15 patents)

17 patents: Sort by Forward Citations

1. 6326675 - Semiconductor device with transparent link area for silicide applications and fabrication thereof (2001-12-04),

2. 6319735 - Photoresist dispense method by compensation for substrate reflectivity (2001-11-20),

3. 6311302 - Method and arrangement for hierarchical control of multiple test access port control modules (2001-10-30),

4. 6309804 - Reducing contamination induced scumming, for semiconductor device, by acid treatment (2001-10-30),

5. 6303192 - Process to improve adhesion of PECVD cap layers in integrated circuits (2001-10-16),

6. 6302771 - CMP pad conditioner arrangement and method therefor (2001-10-16),

7. 6301008 - Arrangement and method for calibrating optical line shortening measurements (2001-10-09),

8. 6287972 - System and method for residue entrapment utilizing a polish and sacrificial fill for semiconductor fabrication (2001-09-11),

9. 6275886 - Microprocessor-based serial bus interface arrangement and method (2001-08-14),

10. 6274445 - Method of manufacturing shallow source/drain junctions in a salicide process (2001-08-14),

11. 6262455 - Method of forming dual gate oxide layers of varying thickness on a single substrate (2001-07-17),

12. 6255226 - Optimized metal etch process to enable the use of aluminum plugs (2001-07-03),

13. 6218735 - Process to improve adhesion of cap layers in intergrated circuits (2001-04-17),

14. 6208004 - Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof (2001-03-27),

15. 6202140 - Memory addressing system and method therefor (2001-03-13),

Company Overview

Philips Semiconductor, Inc., based in Tarrytown, NY, specializes in the development and manufacturing of advanced semiconductor solutions. The company focuses on a variety of technology domains, including integrated circuits, microcontrollers, and digital signal processors, catering to diverse industries such as consumer electronics, automotive, and healthcare. With a commitment to innovation, Philips Semiconductor plays a pivotal role in enhancing connectivity and performance across a wide range of applications globally.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 13 2026

17 Patents

#15 in Tarrytown, NY

#1,101 in New York

#18,894 in US

#35,918 in the World

Tarrytown, NY, United States of America

Philips Semiconductor, Inc.

Forward Citations = 204

28 inventors:

David Howard Ziger (3 out of 42 patents)

Emmanuel De Muizon (2 out of 10 patents)

Rao Venkateswara Annapragada (2 out of 18 patents)

4. Paul S Levy (1 out of 44 patents)

5. David K Cassetti (1 out of 20 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Philips Semiconductor, Inc.. Retrieved from https://idiyas.com/company/philips-semiconductor

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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