The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2001

Filed:

Sep. 29, 1998
Applicant:
Inventor:

Paul S. Levy, Chandler, AZ (US);

Assignee:

Philips Semiconductor, Inc., Tarrytown, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/300 ;
U.S. Cl.
CPC ...
G06F 1/300 ;
Abstract

A microprocessor-based serial bus interface circuit arrangement. The interface circuit arrangement includes a processor, a read-only memory circuit, a random access memory circuit, and a port interface circuit arrangement coupled to a local bus. The processor is configured and arranged to perform selected link layer functions of the IEEE 1394 standard. The read-only memory is configured with instructions for causing the processor to perform the selected link layer functions, and the random access memory is utilized by the link layer software. The port interface circuit arrangement is arranged to couple to the 1394 standard serial bus and transfer data between random access memory and the 1394 bus via the local bus responsive to the processor performing the selected link layer functions.


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