For the Inventor, By the Inventor

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Santa Clara, CA, United States of America

Integrated Memory Technologies, Inc.

USPTO Granted Patents = 20

Forward Citations = 429

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9 inventors (with patents filed for the assignee):

Ching-Shi Jenq (6 out of 6 patents)

Cheng-Chung Tsao (6 out of 6 patents)

Tien-Ler Lin (5 out of 37 patents)

4. Ting P Yen (3 out of 3 patents)

5. Ching Dong Wang (3 out of 3 patents)

6. Ching-Shi Jeng (3 out of 4 patents)

7. Tien L Lin (3 out of 3 patents)

8. Ching-Shi Jeno (1 out of 1 patent)

9. Ben Y Sheen (1 out of 11 patents)

20 patents: Sort by Forward Citations

1. 7407857 - Method of making a scalable flash EEPROM memory cell with notched floating gate and graded source region (2008-08-05),

2. 7199424 - Scalable flash EEPROM memory cell with notched floating gate and graded source region (2007-04-03),

3. 7009244 - Scalable flash EEPROM memory cell with notched floating gate and graded source region (2006-03-07),

4. 6967870 - Combination NAND-NOR memory device (2005-11-22),

5. 6764905 - Method of manufacturing a scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate (2004-07-20),

6. 6621115 - Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate (2003-09-16),

7. 6614715 - Integrated circuit memory device having interleaved read and program capabilities and methods of operating same (2003-09-02),

8. 6556508 - Integrated circuit memory device having interleaved read and program capabilities and methods of operating same (2003-04-29),

9. 6507514 - Integrated circuit memory chip for use in single or multi-chip packaging (2003-01-14),

10. 6496415 - Non-volatile memory device having high speed page mode operation (2002-12-17),

11. 6469955 - Integrated circuit memory device having interleaved read and program capabilities and methods of operating same (2002-10-22),

12. 6377507 - Non-volatile memory device having high speed page mode operation (2002-04-23),

13. 6259625 - Method and apparatus for reducing high current chip erase in flash memories (2001-07-10),

14. 6232185 - Method of making a floating gate memory cell (2001-05-15),

15. 6134149 - Method and apparatus for reducing high current during chip erase in (2000-10-17),

Integrated Memory Technologies, Inc. is a leading semiconductor company specializing in advanced memory solutions. With a focus on innovation and customer satisfaction, we provide high-performance memory products for various industries, including mobile devices, data centers, and consumer electronics. Our portfolio includes DRAM, NAND Flash, and storage solutions that enable faster data processing and storage capabilities. Visit our website to learn more about our cutting-edge memory technologies and how we are shaping the future of computing.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Dec 23 2025

20 Patents

#206 in Santa Clara, CA

#3,805 in California

#15,857 in US

#30,327 in the World

Santa Clara, CA, United States of America

Integrated Memory Technologies, Inc.

Forward Citations = 429

9 inventors:

Ching-Shi Jenq (6 out of 6 patents)

Cheng-Chung Tsao (6 out of 6 patents)

Tien-Ler Lin (5 out of 37 patents)

4. Ting P Yen (3 out of 3 patents)

5. Ching Dong Wang (3 out of 3 patents)

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