Non-volatile memory device having high speed page mode operation

Abstract

A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, a plurality of page latches L, and a plurality of Quick Current Level Translators (QCLT). Each QCLT is connected to and is shared by a plurality of bit lines (32 in the preferred embodiment) through a first column decoder U and is also connected to a plurality of page latches through a second column decoder L. Each page latch is connected to one corresponding output buffer through a third column decoder circuit The page latches are grouped in a plurality of sub-pages. The QCLT performs high speed and high accuracy current-mode comparison and converts the result of comparison into binary codes. These codes are stored in Q-latches U- The QCLT functions as a current-mode analog-to-digital converter (ADC) which converts the memory cell current to binary codes. The data latched in Q-latches will be transferred to page latches for reading out. The cell current sensing devices (QCLT) are separated from the data storage devices (page latches). Hence, the QCLT can perform current sensing operation while the page latch data are being clocked out simultaneously. Within the pitch of 32 bit lines, the QCLT can be designed to achieve high speed sensing, while each page latch has a pitch of 2 bit lines, and shared by two columns of memory cells. High speed sensing makes QCLT more appealing to multi-level cell products. Since multiple sensing iterations are required to determine which levels the cell current located between. Higher speed means less waiting time.