For the Inventor, By the Inventor

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Santa Clara, CA, United States of America

Efinix, Inc.

USPTO Granted Patents = 19

Trademarks = 8

Forward Citations = 12

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14 inventors (with patents filed for the assignee):

Marcel Gort (8 out of 8 patents)

Brett Grady (5 out of 5 patents)

Tony Kai-Kit Ngai (3 out of 3 patents)

4. Ching Lun Yan (3 out of 3 patents)

5. Ho Man Ho (2 out of 2 patents)

6. James G Schleicher (2 out of 45 patents)

7. Yee Hui Lee (2 out of 2 patents)

8. Tony Ngai (1 out of 1 patent)

9. Kara Poon (1 out of 1 patent)

10. Mohamed Faiz Bin Mohamed Iqbal (1 out of 1 patent)

11. Jia Chi Koe (1 out of 1 patent)

12. Kok Yoong Foo (1 out of 1 patent)

13. Joo Jie Ho (1 out of 1 patent)

14. Karn Ming Lau (1 out of 1 patent)

19 patents: Sort by Forward Citations

1. 12750302 - FPGA neighbor output mux direct connections to minimize routing hops (2026-09-29),

2. 12530299 - System and method for primary storage write traffic management (2026-01-20),

3. 12519474 - Adding LUT fracturabiliy to FPGA 4-LUTs using existing adder circuitry (2026-01-06),

4. 12505067 - Configurable logic system and method for pipelined data transfer (2025-12-23),

5. 12355868 - System and method of securing AI model (2025-07-08),

6. 12301232 - FPGA inter-tile control signal sharing (2025-05-13),

7. 12190160 - Neural network accelerator architecture based on custom instruction and DMA on FPGA (2025-01-07),

8. 12147782 - Peripheral tooldual/quad-fracturable digital signal processing block for programmable gate architectures (2024-11-19),

9. 12101092 - Chained programmable delay elements (2024-09-24),

10. 12052160 - FPGA neighbor output mux direct connections to minimize routing hops (2024-07-30),

11. 11791823 - FPGA inter-tile control signal sharing (2023-10-17),

12. 11791821 - Fast FPGA interconnect stitching for wire highways (2023-10-17),

13. 11757439 - Chained programmable delay elements (2023-09-12),

14. 11487927 - Peripheral tool (2022-11-01),

15. 11356101 - Digital signal processing block with reduced pin count for fine-grained programmable gate architecture (2022-06-07),

Company Overview

Efinix, Inc. is a technology company based in Santa Clara, California, specializing in the development of innovative field-programmable gate array (FPGA) solutions. The company focuses on providing high-performance, low-power programmable logic devices that cater to a variety of applications, including artificial intelligence, machine learning, and edge computing. Efinix's unique architecture and design methodologies enable efficient processing capabilities, making it a key player in the evolving landscape of digital design and embedded systems.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 6 2026

19 Patents

#173 in Santa Clara, CA

#4,095 in California

#17,123 in US

#32,623 in the World

Santa Clara, CA, United States of America

Efinix, Inc.

Forward Citations = 12

14 inventors:

Marcel Gort (8 out of 8 patents)

Brett Grady (5 out of 5 patents)

Tony Kai-Kit Ngai (3 out of 3 patents)

4. Ching Lun Yan (3 out of 3 patents)

5. Ho Man Ho (2 out of 2 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Efinix, Inc.. Retrieved from https://idiyas.com/company/efinix

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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