The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2025

Filed:

Feb. 14, 2023
Applicant:

Efinix, Inc., Cupertino, CA (US);

Inventors:

Yee Hui Lee, Bayan Lepas, MY;

Ching Lun Yan, Bayan Lepas, MY;

Assignee:

EFINIX, INC., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); H03K 19/177 (2020.01);
U.S. Cl.
CPC ...
G06F 9/5027 (2013.01); H03K 19/177 (2013.01);
Abstract

The present invention relates to neural network accelerator () in a field programmable gate array (FPGA) which is based on custom instruction interface of an embedded processor in said FPGA and AXI master interface for DMA purposes, wherein said neural network accelerator () comprises of a command control block (), at least one neural network layer accelerator (), a response control block () and an AXI control block (). The amount of neural network layer accelerators () that can be implemented can be configured easily (such as adding a new type of layer accelerator () to said neural network layer accelerator ()) in said FPGA, which makes said invention flexible and scalable.


Find Patent Forward Citations

Lee, Yee. (2025). Neural network accelerator architecture based on custom instruction and dma on fpga (U.S. Patent No. 12190160). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12190160

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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