The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2023

Filed:

Jan. 31, 2022
Applicant:

Efinix, Inc., Santa Clara, CA (US);

Inventors:

Marcel Gort, Toronto, CA;

Tony Ngai, Toronto, CA;

Brett Grady, Toronto, CA;

Kara Poon, Toronto, CA;

Assignee:

EFINIX INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2020.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1737 (2013.01); H03K 19/177 (2013.01); H03K 19/1735 (2013.01);
Abstract

A field programmable gate array (FPGA) has non-highway wire segments for connection to logic blocks, and highway wire segments in a highway network of highways. Each highway has sets of highway wire segments in successive connection. Each successive connection is through a multiplexer. Multiplexers of highways have on-ramps, off-ramps, or both, for programmable connection to wire segments in accordance with programming the FPGA.


Find Patent Forward Citations

Gort, Marcel. (2023). Fast fpga interconnect stitching for wire highways (U.S. Patent No. 11791821). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11791821

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…