The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2025
Filed:
Sep. 19, 2023
Applicant:
Efinix, Inc., Santa Clara, CA (US);
Inventors:
Marcel Gort, Toronto, CA;
Brett Grady, Toronto, CA;
Assignee:
EFINIX, INC., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17728 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17728 (2013.01);
Abstract
Methods and apparatuses to provide FPGA inter-tile control signal sharing are described. In one embodiment, the FPGA inter-tile muxing for control signals is added in a separate tile. In another embodiment, the control signal muxing is distributed among FPGA tiles and shared using a cascaded configuration.
Gort, Marcel. (2025). Fpga inter-tile control signal sharing (U.S. Patent No. 12301232). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12301232
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile