The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2026
Filed:
Jan. 26, 2022
Efinix, Inc., Santa Clara, CA (US);
Marcel Gort, Toronto, CA;
EFINIX, INC., Santa Clara, CA (US);
Abstract
A field programmable gate array (FPGA) has a 4-LUT (lookup table) that has four stages of multiplexers. The 4-LUT is fracturable. The 4-LUT being fracturable includes the capability to implement multiple LUTs in an instance of FPGA programming for functions from a group that includes adder functions and further functions. The 4-LUT has outputs exposed to programmable connection in accordance with FPGA programming. Outputs of the 4-LUT include an output of a first multiplexer in the third stage, an output of a multiplexer in the second stage, and an output of a multiplexer in the second or third stage of the 4-LUT.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile