The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2026
Filed:
Dec. 01, 2021
Applicant:
Efinix, Inc., Santa Clara, CA (US);
Inventor:
Marcel Gort, Toronto, CA;
Assignee:
EFINIX, INC., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/506 (2006.01); G06F 7/501 (2006.01); G06F 30/343 (2020.01); H03K 19/17724 (2020.01);
U.S. Cl.
CPC ...
G06F 7/506 (2013.01); G06F 7/501 (2013.01); G06F 30/343 (2020.01); H03K 19/17724 (2013.01);
Abstract
An adder is implemented in a field programmable gate array (FPGA). The adder has a first ripple carry adder block, for least significant bits of the adder. The adder has a plurality of carry skip adder blocks of differing block sizes. Each block size relates to bit-width of input to a block. The carry skip adder blocks of differing block sizes are for a plurality of bits of the adder. The adder has a second ripple carry adder block, for most significant bits of the adder.
Quick Actions:
Gort, Marcel. (2026). Dynamic block size carry-skip adder construction on fpgas by combining ripple carry adders with routable propagate/generate signals (U.S. Patent No. 12769511). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12769511
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile