Enter assignee name

% Expired Patents = 100.0

Forward Citations = 13

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4 inventors (with patents filed for the assignee):

Thomas E Harrington, Iii (12 out of 33 patents)

Zhijun Qu (5 out of 5 patents)

Robert Kuo-Chang Yang (3 out of 10 patents)

4. John V Spohnheimer (2 out of 2 patents)

12 patents: Sort by Forward Citations

1. 10580884 - Super junction MOS bipolar transistor having drain gaps (2020-03-03),

2. 10134890 - Termination region architecture for vertical power transistors (2018-11-20),

3. 10074735 - Surface devices within a vertical power device (2018-09-11),

4. 9997455 - Device architecture and method for precision enhancement of vertical semiconductor devices (2018-06-12),

5. 9865727 - Device architecture and method for improved packing of vertical field effect devices (2018-01-09),

6. 9837358 - Source-gate region architecture in a vertical power semiconductor device (2017-12-05),

7. 9806186 - Termination region architecture for vertical power transistors (2017-10-31),

8. 9755058 - Surface devices within a vertical power device (2017-09-05),

9. 9589889 - Device architecture and method for precision enhancement of vertical semiconductor devices (2017-03-07),

10. 9496386 - Device architecture and method for improved packing of vertical field effect devices (2016-11-15),

11. 9117899 - Device architecture and method for improved packing of vertical field effect devices (2015-08-25),

12. 9117709 - Device architecture and method for precision enhancement of vertical semiconductor devices (2015-08-25),

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