For the Inventor, By the Inventor

Enter assignee name

Cmk Corporation

Calculating rank

USPTO Granted Patents = 17

% Expired Patents = 58.8

EPO Patents = 1

Forward Citations = 341

Loading Chart...

Loading Chart...

25 inventors (with patents filed for the assignee):

Hiroyasu Jobetto (9 out of 38 patents)

Yutaka Yoshino (4 out of 4 patents)

Takeshi Wakabayashi (2 out of 41 patents)

4. Ichiro Mihara (2 out of 44 patents)

5. Takahiro Shirai (2 out of 2 patents)

6. Shinji Kadono (2 out of 2 patents)

7. Mineo Kawamoto (2 out of 2 patents)

8. Minoru Enomoto (2 out of 2 patents)

9. Masakatsu Goto (2 out of 2 patents)

10. Makoto Araki (2 out of 2 patents)

11. Naoki Toda (2 out of 2 patents)

12. Toshihiro Kido (2 out of 2 patents)

13. Nobuyuki Kageyama (2 out of 2 patents)

14. Daita Kohno (2 out of 2 patents)

15. Jun Yoshizawa (2 out of 2 patents)

17 patents: Sort by Forward Citations

1. 8035979 - Printed wiring board with built-in semiconductor element, and process for producing the same (2011-10-11),

2. 7910405 - Semiconductor device having adhesion increasing film to prevent peeling (2011-03-22),

3. 7894200 - Printed wiring board with built-in semiconductor element, and process for producing the same (2011-02-22),

4. 7867828 - Method of fabricating a semiconductor device including forming an insulating layer with a hard sheet buried therein (2011-01-11),

5. 7709942 - Semiconductor package, including connected upper and lower interconnections (2010-05-04),

6. 7615411 - Semiconductor package including connected upper and lower interconnections, and manufacturing method thereof (2009-11-10),

7. 7608480 - Method of fabricating a semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion (2009-10-27),

8. 7489032 - Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same (2009-02-10),

9. 7445964 - Semiconductor device and method of manufacturing the same (2008-11-04),

10. 7363706 - Method of manufacturing a multilayer printed wiring board (2008-04-29),

11. 7279750 - Semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion (2007-10-09),

12. 7243425 - Printed wiring board and method of manufacturing the same (2007-07-17),

13. 7183639 - Semiconductor device and method of manufacturing the same (2007-02-27),

14. 7087845 - Metal core multilayer printed wiring board (2006-08-08),

15. 5633480 - Printed wiring board having a cover lay laminated on a polyimide resin (1997-05-27),

Company Overview

Cmk Corporation, headquartered in Tokyo, specializes in the development and manufacturing of advanced electronic components and systems. The company focuses on providing innovative solutions for various industries, including automotive, telecommunications, and consumer electronics. With a commitment to research and development, Cmk Corporation aims to enhance the performance and reliability of electronic devices through cutting-edge technology and high-quality production processes. Its expertise positions it as a key player in the evolving landscape of electronic manufacturing.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 27 2026

17 Patents

#1,458 in Tokyo

#3,231 in Japan

#35,974 in the World

Cmk Corporation

Forward Citations = 341

25 inventors:

Hiroyasu Jobetto (9 out of 38 patents)

Yutaka Yoshino (4 out of 4 patents)

Takeshi Wakabayashi (2 out of 41 patents)

4. Ichiro Mihara (2 out of 44 patents)

5. Takahiro Shirai (2 out of 2 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Cmk Corporation. Retrieved from https://idiyas.com/company/cmk

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

Loading…