The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2018
Filed:
Jan. 12, 2017
Intel Corporation, Santa Clara, CA (US);
Ravi Pillarisetty, Portland, OR (US);
Sansaptak Dasgupta, Hillsboro, OR (US);
Niti Goel, Portland, OR (US);
Van H. Le, Portland, OR (US);
Marko Radosavljevic, Beaverton, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Niloy Mukherjee, Portland, OR (US);
Matthew V. Metz, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Benjamin Chu-Kung, Portland, OR (US);
Harold W. Kennel, Portland, OR (US);
Stephen M. Cea, Hillsboro, OR (US);
Robert S. Chau, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.