The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Feb. 03, 2015
Applicant:

Tokyo Electron Limited, Minato-ku, Tokyo, JP;

Inventors:

Kai-Hung Yu, Albany, NY (US);

Toshio Hasegawa, Albany, NY (US);

Tadahiro Ishizaka, Tokyo, JP;

Manabu Oie, Albany, NY (US);

Fumitaka Amano, Albany, NY (US);

Steven Consiglio, Albany, NY (US);

Cory Wajda, Albany, NY (US);

Kaoru Maekawa, Albany, NY (US);

Gert J. Leusink, Albany, NY (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/285 (2006.01); H01L 23/532 (2006.01); C23C 16/04 (2006.01); C23C 16/34 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76846 (2013.01); C23C 16/045 (2013.01); C23C 16/34 (2013.01); H01L 21/28562 (2013.01); H01L 21/76877 (2013.01); H01L 23/53238 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.


Find Patent Forward Citations

Loading…