The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
Oct. 27, 2015
Intel Corporation, Santa Clara, CA (US);
Ravi Pillarisetty, Portland, OR (US);
Been-Yih Jin, Lake Oswego, OR (US);
Benjamin Chu-Kung, Portland, OR (US);
Matthew V. Metz, Portland, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Marko Radosavljevic, Beaverton, OR (US);
Roza Kotlyar, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Niloy Mukherjee, Beaverton, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Robert S. Chau, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.