The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2014
Filed:
Jun. 30, 2010
Chen-yu Tsai, Zhongli, TW;
Shih-hui Wang, Zhonghe, TW;
Chien-ming Chiu, Hsin-Chu, TW;
Chia-ho Chen, Zhubei, TW;
Fang Wen Tsai, Hsin-Chu, TW;
Weng-jin Wu, Hsin-Chu, TW;
Jing-cheng Lin, Hsin-Chu, TW;
Wen-chih Chiou, Miaoli, TW;
Shin-puu Jeng, Hsin-Chu, TW;
Chen-hua Yu, Hsin-Chu, TW;
Chen-Yu Tsai, Zhongli, TW;
Shih-Hui Wang, Zhonghe, TW;
Chien-Ming Chiu, Hsin-Chu, TW;
Chia-Ho Chen, Zhubei, TW;
Fang Wen Tsai, Hsin-Chu, TW;
Weng-Jin Wu, Hsin-Chu, TW;
Jing-Cheng Lin, Hsin-Chu, TW;
Wen-Chih Chiou, Miaoli, TW;
Shin-Puu Jeng, Hsin-Chu, TW;
Chen-Hua Yu, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.