The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2014
Filed:
Sep. 24, 2011
Jin-aun NG, Hsinchu, TW;
Maxi Chang, Banciao, TW;
Jen-sheng Yang, Keelung, TW;
Ta-wei Lin, Minxiong Township, Chiayi County, TW;
Shih-hao Lo, Zhubei, TW;
Chih-yang Yeh, Jhubei, TW;
Hui-wen Lin, Taiping, TW;
Jung-hui Kao, Hsin-Chu, TW;
Yuan-tien Tu, Puzih, TW;
Huan-just Lin, Hsinchu, TW;
Chih-tang Peng, Taipei, TW;
Pei-ren Jeng, Chu-Bei, TW;
Bao-ru Young, Zhubei, TW;
Hak-lay Chuang, Singapore, SG;
Jin-Aun Ng, Hsinchu, TW;
Maxi Chang, Banciao, TW;
Jen-Sheng Yang, Keelung, TW;
Ta-Wei Lin, Minxiong Township, Chiayi County, TW;
Shih-Hao Lo, Zhubei, TW;
Chih-Yang Yeh, Jhubei, TW;
Hui-Wen Lin, Taiping, TW;
Jung-Hui Kao, Hsin-Chu, TW;
Yuan-Tien Tu, Puzih, TW;
Huan-Just Lin, Hsinchu, TW;
Chih-Tang Peng, Taipei, TW;
Pei-Ren Jeng, Chu-Bei, TW;
Bao-Ru Young, Zhubei, TW;
Hak-Lay Chuang, Singapore, SG;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.