The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2007

Filed:

Jul. 13, 2005
Applicants:

Kiyoshi Takekoshi, Nirasaki, JP;

Hisatomi Hosaka, Nirasaki, JP;

Junichi Hagihara, Nirasaki, JP;

Kunihiko Hatsushika, Nirasaki, JP;

Takamasa Usui, Fujisawa, JP;

Hisashi Kaneko, Fujisawa, JP;

Nobuo Hayasaka, Yokosuka, JP;

Yoshiyuki Ido, Ibi-gun, JP;

Inventors:

Kiyoshi Takekoshi, Nirasaki, JP;

Hisatomi Hosaka, Nirasaki, JP;

Junichi Hagihara, Nirasaki, JP;

Kunihiko Hatsushika, Nirasaki, JP;

Takamasa Usui, Fujisawa, JP;

Hisashi Kaneko, Fujisawa, JP;

Nobuo Hayasaka, Yokosuka, JP;

Yoshiyuki Ido, Ibi-gun, JP;

Assignees:

Tokyo Electron Limited, Tokyo, JP;

Kabushiki Kaisha Toshiba, Tokyo, JP;

Ibiden Co., Ltd., Oagki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/06 (2006.01); G01R 31/04 (2006.01); G01R 27/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A reliability evaluation test apparatus of this invention includes a wafer storage section which stores a wafer in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor are totally in electrical contact with each other. The wafer storage section transmits/receives a test signal to/from a measurement section and has a hermetic and heat insulating structure. The wafer storage section has a pressure mechanism which presses the contactor and a heating mechanism which directly heats the wafer totally in contact with the contactor to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.


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