The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2006
Filed:
Feb. 16, 2005
Shyng-tsong Chen, Patterson, NY (US);
Timothy J. Dalton, Ridgefield, CT (US);
Kenneth M. Davis, Newburgh, NY (US);
Chao-kun HU, Somers, NY (US);
Fen F. Jamin, Wappingers Falls, NY (US);
Steffen K. Kaldor, Fishkill, NY (US);
Mahadevaiyer Krishnan, Hopewell Juncion, NY (US);
Kaushik Kumar, Beacon, NY (US);
Michael F. Lofaro, Milton, NY (US);
Sandra G. Malhotra, Beacon, NY (US);
Chandrasekhar Narayan, Hopewell Junction, NY (US);
David L. Rath, Stormville, NY (US);
Judith M. Rubino, Ossining, NY (US);
Katherine L. Saenger, Ossining, NY (US);
Andrew H. Simon, Fishkill, NY (US);
Sean P. E. Smith, Hopewell Junction, NY (US);
Wei-tsu Tseng, Hopewell Junction, NY (US);
Shyng-Tsong Chen, Patterson, NY (US);
Timothy J. Dalton, Ridgefield, CT (US);
Kenneth M. Davis, Newburgh, NY (US);
Chao-Kun Hu, Somers, NY (US);
Fen F. Jamin, Wappingers Falls, NY (US);
Steffen K. Kaldor, Fishkill, NY (US);
Mahadevaiyer Krishnan, Hopewell Juncion, NY (US);
Kaushik Kumar, Beacon, NY (US);
Michael F. Lofaro, Milton, NY (US);
Sandra G. Malhotra, Beacon, NY (US);
Chandrasekhar Narayan, Hopewell Junction, NY (US);
David L. Rath, Stormville, NY (US);
Judith M. Rubino, Ossining, NY (US);
Katherine L. Saenger, Ossining, NY (US);
Andrew H. Simon, Fishkill, NY (US);
Sean P. E. Smith, Hopewell Junction, NY (US);
Wei-tsu Tseng, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.