The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2026
Filed:
Aug. 26, 2022
Intel Corporation, Santa Clara, CA (US);
Chang Wan Han, Portland, OR (US);
Biswajeet Guha, Hillsboro, OR (US);
Vivek Thirtha, Portland, OR (US);
William Hsu, Portland, OR (US);
Ian Yang, Portland, OR (US);
Oleg Golonzka, Beaverton, OR (US);
Kevin J. Fischer, Hillsboro, OR (US);
Suman Dasgupta, Beaverton, OR (US);
Sameerah Desnavi, Hillsboro, OR (US);
Deepak Sridhar, Hillsboro, OR (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer. The various widths are measured in a direction of a semiconductor body between the first source or drain region and the first gate structure.