The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2026
Filed:
Jun. 27, 2022
Intel Corporation, Santa Clara, CA (US);
Debaleena Nandi, Hillsboro, OR (US);
Imola Zigoneanu, Portland, OR (US);
Gilbert Dewey, Beaverton, OR (US);
Anant H. Jahagirdar, Hillsboro, OR (US);
Harold W. Kennel, Portland, OR (US);
Pratik Patel, Portland, OR (US);
Anand S. Murthy, Portland, OR (US);
Chi-Hing Choi, Portland, OR (US);
Mauro J. Kobrinsky, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm.