Debaleena Nandi

Title: Debaleena Nandi: Innovator in Semiconductor Technology

Introduction

Debaleena Nandi is a prominent inventor based in Hillsboro, Oregon, known for her significant contributions to semiconductor technology. With a total of two patents to her name, she has made strides in improving the performance and reliability of transistors.

Latest Patents

Her latest patents include the "Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts." This invention discloses source and drain contacts that enhance contact resistance and interface stability for transistors utilizing silicon and germanium materials. The co-deposited titanium and silicon contact layer significantly improves transistor performance, including switching speed and reliability. Another notable patent is the "Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability." This patent outlines semiconductor devices designed to improve contact resistances, featuring a semiconductor channel, gate stack, and contacts that enhance overall device performance.

Career Highlights

Debaleena Nandi is currently employed at Intel Corporation, where she continues to innovate in the field of semiconductor technology. Her work focuses on developing advanced materials and structures that contribute to the efficiency and effectiveness of electronic devices.

Collaborations

Throughout her career, she has collaborated with notable colleagues, including Chi-hing Choi and Tahir Ghani, to further advance the field of semiconductor research and development.

Conclusion

Debaleena Nandi's contributions to semiconductor technology through her patents and work at Intel Corporation highlight her role as a leading innovator in the industry. Her inventions are paving the way for improved electronic devices and systems.