Intel Corporation

Debaleena Nandi

Tahir Ghani

Gilbert W Dewey

Anand S Murthy

Harold W Kennel

Nazila Haratipour

Chi-hing Choi

Omair Saadat

Adedapo A Oni

Mauro J Kobrinsky

Cory C Bomberger

Jitendra Kumar Jha

Rushabh Shah

Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts

Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability

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Hillsboro, OR, United States of America

Debaleena Nandi